In a conventional vertical high-voltage device, a low-resistivity substrate is normally used to reduce the on-resistance. On the low-resistivity substrate, a high resistivity layer is grown as the drift region (also called as the voltage sustaining layer) by epitaxy or direct wafer bonding. In some vertical devices, there are more epi-layers that need to grow. For instance, in a non-punch-through IGBT, an n+-type (or a p+-type) thin epi-layer is first grown on a p+ (or n+)-substrate, and then a thick n-type epi-layer is grown on the thin epi-layer.
FIG. 1 shows a cross-sectional view of the device structure presented in Kitamura et al., U.S. Pat. No. 5,844,275 (1998). A p-well is formed in a portion of the surface of a p-type substrate. A trench is formed in the p-well and filled with an insulator material such as SiO2. An n-type drift region is formed surrounding the trench from the side of the sidewalls to the bottom wall thereof. A p-type source-body region and an n-type source region are formed in a portion of the surface of the p-well at one side of the trench. An electrode is then formed so as to be in contact to the n-type source region and p-type source-body region. An n-type drain region is formed at the other side of the trench by diffusion or ion implantation. An electrode is deposited so as to be in contact to the drain region. A poly-silicon gate is deposited on the gate oxide grown on the substrate from the trench to the n-type source region. A conductive channel is formed by applying a positive bias larger than the threshold voltage on the gate to turn the device on.
FIG. 2 shows the device structure in KaInitsky et al., U.S. Pat. No. 6,525,397 B1 (2003). It is a high-voltage MOS for programming an integrated fuse element. N-wells are formed in parts of the surface of a p-type substrate. Trenches are formed in parts of the surface of the n-wells. U-shape voltage sustaining regions are defined based on trench isolation. A source region is formed by an n+ doping at one side of the trench in a portion of the surface of the p-substrate. A drain region is formed by an n+ doping at the other side of the trench in a portion of the surface of the n-well. A p-n junction isolation between the high-voltage device and other devices is realized through the n-well and the p-substrate formed.
FIG. 3 shows a cross-sectional view of the device structure utilizing a trench presented in Kitamura et al., U.S. Pat. No. 6,998,680 B2 (2006). It is similar to the device shown in FIG. 1. When a voltage higher than the threshold voltage is applied to the gate, the device is turned on and a current flows from the drain electrode, through the drain region, the U-shape drift region, the channel and the source region, and eventually to the source electrode.
FIG. 4 shows a cross-sectional view of a lateral MOS structure based on a trench in Baliga, B. J., U.S. Pat. No. 5,434,435 (1995). The polycrystalline silicon gate is formed in a portion of one edge inside the trench. The conductive channel is formed along the sidewall of the trench in the on-state. An intermediate layer is used for isolation between the drift region and the substrate. Two methods of isolation can be applied in this structure. For dielectric isolation, an oxide can be used as the intermediate layer grown on an n-type or a p-type substrate. For junction isolation, a p-type Si can be used as the intermediate layer.
It is noticed the drift region in above devices is doped oppositely to the doping type of the substrate, leading to a more complex process. Furthermore, the device feature region, including the source region, the source-body region and part of the gate region is formed outside of the U-shape drift region, causing a large area.
Although trench etching is a mature process in modern technology of micro-electronics, the method of forming the gate in Baliga, B. J., U.S. Pat. No. 5,434,435 (1995) still makes the process more complex. In addition, another direct wafer bonding or epitaxy should be conducted for growing the intermediate layer for isolation, leading to a higher cost.
Generally speaking, many devices are composed of two device feature regions, and a drift region is between the two feature regions. Under a reverse bias, the drift region becomes a voltage-sustaining region. In a conventional vertical device, one device feature region is formed in the surface of the substrate and the other is formed in the bottom of the substrate. For example, in a high-voltage n-MOS, the drift region is a lightly doped n-type region and its drain region is a heavily doped n+-region. The drain region can be considered as one of the device feature regions. For a non-punch-through IGBT with an n-MOS included, one of its device feature regions is the n-MOS formed in the surface of the substrate and the other device feature region is the thin n+-layer on the p+-substrate. The thick n−-epi-layer between the two device feature regions is the drift region. Obviously, the implementation of the latter device feature region causes a more complex process and a higher fabrication cost.
Besides, in order to reduce the injection of the minorities to the drift region and thus to realize a shorter turn-off time, normally, the injection efficiency should be taken into account in design the material parameters. There is a trade-off between the on-voltage and the turn-off time. Even such a trade-off is optimized, it is still not able to eliminate the injection of the minorities during the turn-off process entirely.